A binary tree based methodology for designing an application specific network-on-chip (ASNOC)

Yuan Long Jeang, Jer Min Jou, Win Hsien Huang

研究成果: Article同行評審

8 引文 斯高帕斯(Scopus)

摘要

In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.

原文English
頁(從 - 到)3531-3538
頁數8
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
發行號12
DOIs
出版狀態Published - 2005 12月

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程
  • 應用數學

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