A BIST scheme for FPGA interconnect delay faults

Chun Chieh Wang, Jing Jia Liou, Yen Lin Peng, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)


In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.

主出版物標題Proceedings - 23rd IEEE VLSI Test Symposium, VTS 2005
出版狀態Published - 2005 12月 1
事件23rd IEEE VLSI Test Symposium, VTS 2005 - Palm Springs, CA, United States
持續時間: 2005 5月 12005 5月 5


名字Proceedings of the IEEE VLSI Test Symposium


Conference23rd IEEE VLSI Test Symposium, VTS 2005
國家/地區United States
城市Palm Springs, CA

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程


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