A built-in self-repair design for RAMs with 2-D redundancy

Jin Fu Li, Jen Chieh Yeh, Rei Fu Huang, Cheng Wen Wu

研究成果: Article同行評審

62 引文 斯高帕斯(Scopus)

摘要

This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K × 64 SRAM.

原文English
頁(從 - 到)742-745
頁數4
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
13
發行號6
DOIs
出版狀態Published - 2005 六月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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