A built-in self-repair scheme for NOR-type flash memory

Yu Ying Hsiao, Chao Hsun Chen, Cheng Wen Wu

研究成果: Conference contribution

15 引文 斯高帕斯(Scopus)

摘要

The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.

原文English
主出版物標題Proceedings - 24th IEEE VLSI Test Symposium
頁面114-119
頁數6
DOIs
出版狀態Published - 2006 十一月 22
事件24th IEEE VLSI Test Symposium - Berkeley, CA, United States
持續時間: 2006 四月 302006 五月 4

出版系列

名字Proceedings of the IEEE VLSI Test Symposium
2006

Other

Other24th IEEE VLSI Test Symposium
國家/地區United States
城市Berkeley, CA
期間06-04-3006-05-04

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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