TY - GEN
T1 - A built-in self-repair scheme for NOR-type flash memory
AU - Hsiao, Yu Ying
AU - Chen, Chao Hsun
AU - Wu, Cheng Wen
PY - 2006/11/22
Y1 - 2006/11/22
N2 - The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.
AB - The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.
UR - https://www.scopus.com/pages/publications/33751072414
UR - https://www.scopus.com/pages/publications/33751072414#tab=citedBy
U2 - 10.1109/VTS.2006.5
DO - 10.1109/VTS.2006.5
M3 - Conference contribution
AN - SCOPUS:33751072414
SN - 0769525148
SN - 9780769525143
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 114
EP - 119
BT - Proceedings - 24th IEEE VLSI Test Symposium
T2 - 24th IEEE VLSI Test Symposium
Y2 - 30 April 2006 through 4 May 2006
ER -