A Built-in Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy

Jin Fu Li, Jen Chieh Yeh, Rei Fu Huang, Cheng Wen Wu, Peir Yuan Tsai, Archer Hsu, Eugene Chow

研究成果: Conference article同行評審

60 引文 斯高帕斯(Scopus)

摘要

Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes; the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead - about 4.6% for an 8K×64 SRAM.

原文English
頁(從 - 到)393-402
頁數10
期刊IEEE International Test Conference (TC)
出版狀態Published - 2003 十一月 6
事件Proceedings International Test Conference 2003 - Charlotte, NC, United States
持續時間: 2003 九月 302003 十月 2

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程
  • 硬體和架構

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