A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Chih Wea Wang, Ruey Shing Tzeng, Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu, Shi Yu Huang, Shyh Horng Lin, Hsin Po Wang

研究成果: Conference article同行評審

17 引文 斯高帕斯(Scopus)

摘要

Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SOC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

原文English
頁(從 - 到)103-108
頁數6
期刊Proceedings of the Asian Test Symposium
出版狀態Published - 2001 十二月 1
事件Proceedings of the 10th Asian Test Symposium - Kyoto, Japan
持續時間: 2001 十一月 192001 十一月 21

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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