A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Yu Jen Huang, Jin Fu Li, Ji Jan Chen, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

研究成果: Conference contribution

68 引文 斯高帕斯(Scopus)

摘要

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18m CMOS technology for a 1632 TSV array in which each TSV cell size is 45m2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

原文English
主出版物標題Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
頁面20-25
頁數6
DOIs
出版狀態Published - 2011 七月 1
事件2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
持續時間: 2011 五月 12011 五月 5

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference2011 29th IEEE VLSI Test Symposium, VTS 2011
國家United States
城市Dana Point, CA
期間11-05-0111-05-05

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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