TY - JOUR
T1 - A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique
AU - Wang, Jia Ching
AU - Hung, Tsung Chih
AU - Kuo, Tai Haur
N1 - Funding Information:
Manuscript received April 24, 2020; revised June 28, 2020; accepted July 31, 2020. Date of publication August 21, 2020; date of current version November 24, 2020. This article was approved by Guest Editor John P. Keane. This work was supported by the Ministry of Science and Technology (MOST) of Taiwan. (Corresponding author: Tai-Haur Kuo.) The authors are with the Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan (e-mail: thkuo@ee.ncku.edu.tw).
PY - 2020/12
Y1 - 2020/12
N2 - This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted-averaging correlated level shifting (WACLS) technique. For a closed-loop residue amplification, the error voltage due to the finite operational amplifier (opamp) gain can be ideally removed by the proposed WACLS technique with a low-gain opamp. In addition, the opamp bandwidth degradation, by an extra level-shift capacitor (CLS) in two-phase amplification CLS-based circuits, can be relaxed and minimized in WACLS. Furthermore, a speed-enhancement scheme is provided to alleviate the speed degradation owing to one extra amplification phase and long bit-cycling time from two-phase amplification and SAR circuits, respectively. A modified reference swapping (RS) technique is applied to diminish the capacitor mismatch error without any calibration. A quick startup ring amplifier design is introduced for duty-cycled control power saving. The chip is implemented in the 28-nm CMOS technology and occupies an active area of 0.018 mm2. At 100 MS/s and Nyquist-rate input, the measured SNDR is 71.7 dB with 0.7-mW power consumption only. The calibration-free ADC achieves Walden and Schreier figure-of-merit of 2.2 fJ/conversion-step and 180.2 dB, respectively. Compared with the prior-art ADCs with sampling frequency > 100 MS/s and SNDR > 65 dB, this work advances the state-of-the-art by 3 × and 5.3 dB, respectively.
AB - This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted-averaging correlated level shifting (WACLS) technique. For a closed-loop residue amplification, the error voltage due to the finite operational amplifier (opamp) gain can be ideally removed by the proposed WACLS technique with a low-gain opamp. In addition, the opamp bandwidth degradation, by an extra level-shift capacitor (CLS) in two-phase amplification CLS-based circuits, can be relaxed and minimized in WACLS. Furthermore, a speed-enhancement scheme is provided to alleviate the speed degradation owing to one extra amplification phase and long bit-cycling time from two-phase amplification and SAR circuits, respectively. A modified reference swapping (RS) technique is applied to diminish the capacitor mismatch error without any calibration. A quick startup ring amplifier design is introduced for duty-cycled control power saving. The chip is implemented in the 28-nm CMOS technology and occupies an active area of 0.018 mm2. At 100 MS/s and Nyquist-rate input, the measured SNDR is 71.7 dB with 0.7-mW power consumption only. The calibration-free ADC achieves Walden and Schreier figure-of-merit of 2.2 fJ/conversion-step and 180.2 dB, respectively. Compared with the prior-art ADCs with sampling frequency > 100 MS/s and SNDR > 65 dB, this work advances the state-of-the-art by 3 × and 5.3 dB, respectively.
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U2 - 10.1109/JSSC.2020.3015863
DO - 10.1109/JSSC.2020.3015863
M3 - Article
AN - SCOPUS:85097242876
VL - 55
SP - 3271
EP - 3280
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 12
M1 - 9173774
ER -