A closed-form delay formula for on-chip RLC interconnects in current-mode signaling

Current-mode signaling significantly increases the bandwidth of on-chip interconnects compared to voltage mode signaling and reduces the overall propagation delay. A delay formula (line and load delay) for current mode is necessary for estimation of delay and bandwidth for VLSI systems. The inductance effect of interconnects is more dominant in sub-micron technology. So a RC approximation results in significant error in delay estimation. This paper presents a closed-form delay formula for on-chip RLC interconnects for current mode signaling. The delay formula reported herein is derived based on the modified nodal analysis (MNA) formulation and an equivalent lumped model representation of inductance effects. Compared to computationally intensive methods, this method results in a simple yet accurate expression by 'absorbing' the inductance into the RC model. The formula is verified via HSPICE simulations and is 5% accuracy over a wide range of interconnect parameters. The accuracy of the expression under different ranges of parameters is discussed, enabling this to be used as design tool.