A CMOS analog vector quantizer for pattern recognition

Yu Cherng Hung, Bin Da Liu

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

A linear mean-absolute-difference (MAD) cell is designed. Based on this cell and winner-take-all circuit, we propose a parallel analog vector-quantizer for pattern recognition. The experimental circuit is constituted by one input pattern and 16 template patterns with 16 elements. This circuit had been simulated using 0.5 μm CMOS technology by HSPICE. The results show that a pattern can be correctly identified if the difference of the MAD distance metric is larger or smaller than 100 mV. Simulation results demonstrate 250 ns identified time and 16 mW power dissipation for single 3.3 V voltage supply.

原文English
主出版物標題AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
發行者Institute of Electrical and Electronics Engineers Inc.
頁面112-115
頁數4
ISBN(列印)0780357051, 9780780357051
DOIs
出版狀態Published - 1999 1月 1
事件1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
持續時間: 1999 8月 231999 8月 25

出版系列

名字AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
國家/地區Korea, Republic of
城市Seoul
期間99-08-2399-08-25

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 電子、光磁材料

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