This paper proposes efficient methods to reduce the cost and power consumption of flash analog-to-digital converters (ADCs). An auto-zeroing technique is incorporated with a low-complexity low-power capacitor averaging network for efficient offset cancellation and signal interpolation. Therefore, the cost and power consumption of flash ADCs can be efficiently reduced. A compact low-power 8-bit 500MS/s flash ADC with the above features is fabricated with 0.18μm CMOS process. The active area occupies 0.35mm2 and its measured power at 500MS/s is 160mW from a 1.8V supply. Measured signal-to-noise-plus-distortion ratio (SNDR) of the ADC is 40dB with 200MHz input frequency sampled at 500MS/s. The figure-of-merit (FOM) is 4.17pJ/conversion-step, which is the best compared to published 0.18μm 8-bit flash ADCs. Further, the power consumption and active area are the smallest compared with state-of-the-art 0.18μm 8-bit high-speed ADCs.