A compact SPICE model for bipolar resistive switching memory

Kai Hsiang Hsu, Wei Wen Ding, Meng Hsueh Chiang

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

In this paper, we successfully develop a compact model for bipolar resistive switching memory using Verilog-A. Fundamental I-V characteristics of RRAM are physically and yet simply represented by this model. Since the Verilog-A modeling is flexible and portable for many circuit simulators, the proposed modeling technique can be widely used.

原文English
主出版物標題2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
出版狀態Published - 2013 十二月 23
事件2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
持續時間: 2013 六月 32013 六月 5

出版系列

名字2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
國家Hong Kong
城市Hong Kong
期間13-06-0313-06-05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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