TY - GEN
T1 - A complete logic BIST technology with no storage requirement
AU - Lien, Wei Cheng
AU - Lee, Kuen-Jong
PY - 2010/12/1
Y1 - 2010/12/1
N2 - Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.
AB - Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.
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U2 - 10.1109/ATS.2010.31
DO - 10.1109/ATS.2010.31
M3 - Conference contribution
AN - SCOPUS:79951651578
SN - 9780769542485
T3 - Proceedings of the Asian Test Symposium
SP - 129
EP - 134
BT - Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
T2 - 2010 19th IEEE Asian Test Symposium, ATS 2010
Y2 - 1 December 2010 through 4 December 2010
ER -