A complete logic BIST technology with no storage requirement

Wei Cheng Lien, Kuen-Jong Lee

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.

原文English
主出版物標題Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
頁面129-134
頁數6
DOIs
出版狀態Published - 2010 十二月 1
事件2010 19th IEEE Asian Test Symposium, ATS 2010 - Shanghai, China
持續時間: 2010 十二月 12010 十二月 4

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Other

Other2010 19th IEEE Asian Test Symposium, ATS 2010
國家China
城市Shanghai
期間10-12-0110-12-04

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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