The march algorithm based built-in self-test (BIST) schemes have been widely used to test memory chips (cores). Conventional methods which use binary counters to generate the addresses may require large routing area when the addresses are to be broadcast to multiple memory cores. In this paper we propose to use linear feedback shift registers (LFSRs) to generate the memory addresses which can be serially applied to the memory cores under test and thus the routing area overhead can be greatly reduced. We have designed a complete up/down LFSR which can generate complete march addresses, including all 2 n up and 2n down sequences. Also theoretic analysis has been done which guarantees the transitions from up to down and down to up sequences can all be smoothly carried out such that the memory under test can receive a different address per clock cycle even during the transitions.
|頁（從 - 到）
|Records of the IEEE International Workshop on Memory Technology, Design and Testing
|Published - 2005 12月 9
|Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan
持續時間: 2005 8月 3 → 2005 8月 5
All Science Journal Classification (ASJC) codes