A complete memory address generator for scan based march algorithms

Wei Lun Wang, Kuen-Jong Lee

研究成果: Conference article同行評審

10 引文 斯高帕斯(Scopus)

摘要

The march algorithm based built-in self-test (BIST) schemes have been widely used to test memory chips (cores). Conventional methods which use binary counters to generate the addresses may require large routing area when the addresses are to be broadcast to multiple memory cores. In this paper we propose to use linear feedback shift registers (LFSRs) to generate the memory addresses which can be serially applied to the memory cores under test and thus the routing area overhead can be greatly reduced. We have designed a complete up/down LFSR which can generate complete march addresses, including all 2 n up and 2n down sequences. Also theoretic analysis has been done which guarantees the transitions from up to down and down to up sequences can all be smoothly carried out such that the memory under test can receive a different address per clock cycle even during the transitions.

原文English
頁(從 - 到)83-88
頁數6
期刊Records of the IEEE International Workshop on Memory Technology, Design and Testing
出版狀態Published - 2005 十二月 9
事件Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan
持續時間: 2005 八月 32005 八月 5

All Science Journal Classification (ASJC) codes

  • 媒體技術

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