A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

Y. T. Tang, C. L. Fan, Y. C. Kao, N. Modolo, C. J. Su, T. L. Wu, K. H. Kao, P. J. Wu, S. W. Hsaio, A. Useinov, Pin Su, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

研究成果: Conference contribution

摘要

This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o-and t-phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t-to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed.

原文English
主出版物標題2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T222-T223
ISBN(電子)9784863487178
DOIs
出版狀態Published - 2019 六月
事件39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan
持續時間: 2019 六月 92019 六月 14

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2019-June
ISSN(列印)0743-1562

Conference

Conference39th Symposium on VLSI Technology, VLSI Technology 2019
國家Japan
城市Kyoto
期間19-06-0919-06-14

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此

Tang, Y. T., Fan, C. L., Kao, Y. C., Modolo, N., Su, C. J., Wu, T. L., ... Wang, Y. H. (2019). A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs. 於 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (頁 T222-T223). [8776508] (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776508