A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node

Y. T. Tang, C. J. Su, Y. S. Wang, K. H. Kao, T. L. Wu, P. J. Sung, F. J. Hou, C. J. Wang, M. S. Yeh, Y. J. Lee, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE∼2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.

原文English
主出版物標題2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面45-46
頁數2
ISBN(電子)9781538642160
DOIs
出版狀態Published - 2018 十月 25
事件38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
持續時間: 2018 六月 182018 六月 22

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2018-June
ISSN(列印)0743-1562

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
國家United States
城市Honolulu
期間18-06-1818-06-22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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