A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Cheng-Wen Wu, P.-W. Luo, C.-K. Chen, Y.-H. Sung, W. Wu, H.-C. Shih, C.-H. Lee, K.-H. Lee, M.-W. Li, M.-C. Lung, C.-N. Lu, Y.-F. Chou, P.-L. Shih, C.-H. Ke, C. Shiah, P. Stolt, S. Tomishima, D.-M. Kwai, B.-D. Rong, N. LuS.-L. Lu

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)
原文English
主出版物標題IEEE Symp. VLSI Circuits (VLSI)
出版狀態Published - 2015 六月

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