A configurable AES processor for enhanced security

Chih Pin Su, Chia Lung Horng, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)

摘要

We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to 2 19 different AES block cipher schemes within a reasonable hardware cost. Data can he encrypted not only with secret keys and initial vectors, but also by different block ciphers during the communication. A novel on-the-fly key expansion design is also proposed for.128-, 192-, and 256-bit keys. Our unified hardware can run both the original AES algorithm and the extended AES algorithm. The proposed processor design has been fabricated by a 0.25μm CMOS process, with a silicon area of 6.93mm 2-about 200.5K equivalent gates. Under a 66MHz clock, the throughput rate for both the ECB and CBC operation modes are S44.8Mbps, 704Mbps, and 603.4Mbps for 128-bit, 192-bit, and 256-bit keys, respectively.

原文English
主出版物標題Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
發行者Institute of Electrical and Electronics Engineers Inc.
頁面361-366
頁數6
ISBN(列印)0780387368, 9780780387362
DOIs
出版狀態Published - 2005 十二月 1
事件2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
持續時間: 2005 一月 182005 一月 21

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
國家/地區China
城市Shanghai
期間05-01-1805-01-21

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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