A current reuse quadrature GPS receiver in 0.13 μm CMOS

Kuang-Wei Cheng, Karthik Natarajan, David J. Allstot

研究成果: Article同行評審

41 引文 斯高帕斯(Scopus)

摘要

A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT Σ Δ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ MHz frequency offset with quadrature error less than 1°.

原文English
文章編號5419194
頁(從 - 到)510-523
頁數14
期刊IEEE Journal of Solid-State Circuits
45
發行號3
DOIs
出版狀態Published - 2010 三月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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