Building a test platform within an SOC design to simplify the SOC test problem has recently been shown to be a very effective test methodology. In this paper, a design automation system, called DASTEP (Design Automation System for SOC Test Platform), is presented to help a user build a test platform and incorporate his/her IP designs into the platform. DASTEP provides an interactive mode to allow the user to modify IP cores into testable ones and integrate them into the test platform. To standardize the test procedure, DASTEP furnishes the capability of wrapping cores with the 1149.1 or 1500 standard wrappers. DASTEP also provides a 1149.1-compatible hierarchical test control architecture such that each hierarchical core can be tested in a hierarchical manner. A sophisticated test-access-mechanism (TAM) controller along with the required test bus can be automatically synthesized which form the kernel of the test platform. DASTEP also creates an appropriate simulation environment that allows the simulation of the entire test flow, making the verification of both core design and test plan possible. All the capabilities of DASTEP are provided via friendly graphic user interface, which makes DASTEP a powerful, yet very easy-to-use electronic design automation (EDA) system for SOC testing.
|頁（從 - 到）||219-227|
|期刊||International Journal of Electrical Engineering|
|出版狀態||Published - 2007 6月|
All Science Journal Classification (ASJC) codes