A design of linearity built-in self-test for current-steering DAC

Hsin Wen Ting, Soon Jyh Chang, Su Ling Huang

研究成果: Article同行評審

12 引文 斯高帕斯(Scopus)

摘要

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

原文English
頁(從 - 到)85-94
頁數10
期刊Journal of Electronic Testing: Theory and Applications (JETTA)
27
發行號1
DOIs
出版狀態Published - 2011 二月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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