TY - JOUR
T1 - A Digital Power Factor Controller for Primary-Side-Regulated LED Driver
AU - Lee, Yi Jing
AU - Niou, Chun Ping
AU - Chen, Chun Yu
AU - Tsai, Chien Hung
N1 - Funding Information:
This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 108-2221-E-006-145-MY2, and in part by the Leadtrend Technology.
Publisher Copyright:
© 2013 IEEE.
PY - 2020
Y1 - 2020
N2 - In this study, a digital primary-side controller for a flyback light-emitting diode driver with superior line regulation, high power factor (PF), and low total harmonic distortion (THD) was proposed. Conventional constant on-Time control is hampered by input current distortion, leading to high THD. To achieve high PF and low THD, a digital switching frequency limiter with quasi-resonant control was proposed. In addition, owing to the turn-off delay of the MOSFET and propagation delay of the feedback signals, a primary-side-controlled flyback converter experiences poor line regulation. To achieve superior line regulation, delay compensation was proposed and analyzed. A digital controller was realized using a field-programmable gate array and was applied to an input voltage of 90-264~V_{\mathrm {ac}} and an output current of 1 A in a hardware prototype to verify the feasibility of the proposed control solution. The experimental results indicate that line regulation was within ±3%, PF was higher than 0.95, and THD was lower than 5% at universal input voltage.
AB - In this study, a digital primary-side controller for a flyback light-emitting diode driver with superior line regulation, high power factor (PF), and low total harmonic distortion (THD) was proposed. Conventional constant on-Time control is hampered by input current distortion, leading to high THD. To achieve high PF and low THD, a digital switching frequency limiter with quasi-resonant control was proposed. In addition, owing to the turn-off delay of the MOSFET and propagation delay of the feedback signals, a primary-side-controlled flyback converter experiences poor line regulation. To achieve superior line regulation, delay compensation was proposed and analyzed. A digital controller was realized using a field-programmable gate array and was applied to an input voltage of 90-264~V_{\mathrm {ac}} and an output current of 1 A in a hardware prototype to verify the feasibility of the proposed control solution. The experimental results indicate that line regulation was within ±3%, PF was higher than 0.95, and THD was lower than 5% at universal input voltage.
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U2 - 10.1109/ACCESS.2020.2966016
DO - 10.1109/ACCESS.2020.2966016
M3 - Article
AN - SCOPUS:85079772839
SN - 2169-3536
VL - 8
SP - 21813
EP - 21822
JO - IEEE Access
JF - IEEE Access
M1 - 8957052
ER -