A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Jih Ren Goh, Yen Long Lee, Soon Jyh Chang

研究成果: Conference contribution

摘要

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519∗0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

原文English
主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479962754
DOIs
出版狀態Published - 2015 五月 28
事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
持續時間: 2015 四月 272015 四月 29

出版系列

名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Other

Other2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家/地區Taiwan
城市Hsinchu
期間15-04-2715-04-29

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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