A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Yen Long Lee, Yu Po Cheng, Soon Jyh Chang, Hsin Wen Ting

研究成果: Article同行評審

摘要

Editor's note: Analysis of jitter tolerance of CDR circuit is important for high-speed serial link design. This article presents a simple yet effective method for evaluating the tracking capability of CDR, which is applied to the analysis.-Youngsoo Shin, KAIST.

原文English
文章編號8039277
頁(從 - 到)63-73
頁數11
期刊IEEE Design and Test
35
發行號1
DOIs
出版狀態Published - 2018 二月

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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