TY - GEN
T1 - A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer
AU - Hsu, Tien Feng
AU - Huang, Chun Po
AU - Chao, I. Jen
AU - Chang, Soon Jyh
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/5/28
Y1 - 2015/5/28
N2 - This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.
AB - This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.
UR - https://www.scopus.com/pages/publications/84936966531
UR - https://www.scopus.com/pages/publications/84936966531#tab=citedBy
U2 - 10.1109/VLSI-DAT.2015.7114518
DO - 10.1109/VLSI-DAT.2015.7114518
M3 - Conference contribution
AN - SCOPUS:84936966531
T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Y2 - 27 April 2015 through 29 April 2015
ER -