A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits

Yi Wei Huang, Tai Haur Kuo, Szu Yu Huang, Kuan Yu Fang

研究成果: Article

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a four-phase buck converter with capacitor-current-sensor (CCS) calibration for load-transient-response optimization that targets the theoretically minimal output-voltage undershoot ΔVUS, overshoot ΔVOS, and settling time tS when large and rapid load-current transients ΔIload occur. The proposed CCS calibration calibrates the CCS' equivalent impedance to emulate a scaled replica of the output capacitor's impedance ZCo. Thus, the CCS can accurately sense the output-capacitor current ICo despite ZCo variations due to different output voltages, fabrication variations, and printed-circuit-board parasitics. Moreover, a load-transient optimizer is proposed to utilize the accurately sensed ICo to instantly detect the large and rapid ΔIload, and synchronously control the charging and discharging durations of the output inductors in all four phases, resulting in small ΔVUS/ΔVOS and short tS. The converter is implemented in a 0.18-μm CMOS process with 1.93-mm2 chip area. For a 1.8-A/5-ns step-up (step-down) ΔIload, the measured ΔVUS (ΔVOS) and tS are 92 mV (75 mV) and 133 ns (110 ns), respectively. Compared with other state-of-the-arts, both the measured ΔVUS (ΔVOS) and tS in this paper are the closest to their respective theoretical limits, i.e., the fastest load-transient response with the smallest ΔVUS (ΔVOS) and the shortest tS under the same input voltage, output voltage, output inductance, and output capacitance.

原文English
文章編號8148964
頁(從 - 到)552-568
頁數17
期刊IEEE Journal of Solid-State Circuits
53
發行號2
DOIs
出版狀態Published - 2018 二月

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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