A fuzzy neural network chip based on systolic array architecture

Jiahn Jung Chen, Yau-Hwang Kuo, Cheng I. Kao

研究成果: Conference contribution

摘要

A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain.

原文English
主出版物標題Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
發行者IEEE Computer Society
頁面577-580
頁數4
ISBN(電子)0780307682
DOIs
出版狀態Published - 1992 一月 1
事件5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
持續時間: 1992 九月 211992 九月 25

出版系列

名字Proceedings of International Conference on ASIC
ISSN(列印)2162-7541
ISSN(電子)2162-755X

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
國家/地區United States
城市Rochester
期間92-09-2192-09-25

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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