TY - JOUR
T1 - A fuzzy search block-matching chip for motion estimation
AU - Chen, Pei Yin
N1 - Funding Information:
This research was supported in part by the National Science Council, Republic of China, under the Grant NSC-89-2213-E-218-036.
Copyright:
Copyright 2005 Elsevier B.V., All rights reserved.
PY - 2002/11
Y1 - 2002/11
N2 - Fuzzy logic has been successfully applied to control vague, incomplete, complex, and ill-defined systems. With the help of fuzzy inference, an efficient inter-block/inter-frame fuzzy search (IIFS) algorithm for block motion estimation is proposed. By using the inter-block and inter-frame correlations, IIFS can determine the motion vectors of image blocks quickly and correctly. However, the IIFS algorithm is not suitable for hardware implementation due to very irregular data flow. Hence, in this paper we propose a modified inter-block/inter-frame fuzzy search (MIIFS) algorithm that can be easily realized with VLSI technology. With 0.6 μm CMOS technology, the MIIFS chip has a die size of 4.1 × 4.1 mm2 and 108 K transistors. It can work with a clock rate of 67 MHz, and yield a running speed that can support the MPEG video resolution (720 pixels × 480 lines, 30 frames/s) in real time.
AB - Fuzzy logic has been successfully applied to control vague, incomplete, complex, and ill-defined systems. With the help of fuzzy inference, an efficient inter-block/inter-frame fuzzy search (IIFS) algorithm for block motion estimation is proposed. By using the inter-block and inter-frame correlations, IIFS can determine the motion vectors of image blocks quickly and correctly. However, the IIFS algorithm is not suitable for hardware implementation due to very irregular data flow. Hence, in this paper we propose a modified inter-block/inter-frame fuzzy search (MIIFS) algorithm that can be easily realized with VLSI technology. With 0.6 μm CMOS technology, the MIIFS chip has a die size of 4.1 × 4.1 mm2 and 108 K transistors. It can work with a clock rate of 67 MHz, and yield a running speed that can support the MPEG video resolution (720 pixels × 480 lines, 30 frames/s) in real time.
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U2 - 10.1016/S0167-9260(02)00046-9
DO - 10.1016/S0167-9260(02)00046-9
M3 - Article
AN - SCOPUS:0036858533
SN - 0167-9260
VL - 32
SP - 133
EP - 147
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 1-2
ER -