A gm/ID-based synthesis tool for pipelined analog to digital converters

Ya Ting Shyu, Cheng Wu Lin, Jin Fu Lin, Soon Jyh Chang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面299-302
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

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