A hardware design approach for merge-sorting network

Chun Yueh Huang, Gwo Jeng Yu, Bin Da Liu

研究成果: Conference contribution

13 引文 斯高帕斯(Scopus)

摘要

In this paper, a hardware design methodology for merge-sorting networks, which uses a fixed size Batcher's sorting network, a data memory module and a memory addressing controller, is proposed. In this method, only by adjusting the data flow of the memory addressing controller, the amount of sorting data can be extended easily. Particularly, the adjustment of data flow is quite regular. Therefore, the proposed method has the following merits: low complexity of parallel sorting networks, low hardware fabrication cost, high extensibility, high regularity and no extra data memory space needed. For verifying the proposed approach, a 128-item merge-sorting network has been designed and simulated by Verilog VHDL.

原文English
主出版物標題ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
頁面534-537
頁數4
DOIs
出版狀態Published - 2001 十二月 1
事件2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
持續時間: 2001 五月 62001 五月 9

出版系列

名字ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
國家Australia
城市Sydney, NSW
期間01-05-0601-05-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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