A hierarchical interface design methodology and models for SOC IP integration

Jer-Min Jou, Shiann Rong Kuang, Kuang Ming Wu

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

A key aspect of an IP core's marketability is its ability to be easily integrated across a wide variety of interfaces. In this paper, we propose an efficient hierarchical interface design methodology and models so that a designer can quickly design an IP core's interface, which can be easily integrated into any interface/bus architecture. The proposed methodology and models have been applied to design an MP3 decoder with different interfaces: an ISA bus interface and a PCI bus interface. The results demonstrate that the methodology and models result in easy IP integration and only a little performance overhead.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
出版狀態Published - 2002

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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