A hierarchical test methodology for systems on chip

Jin Fu Li; Hsin Jung Huang; Jeng Bin Chen; Chih Pin Su; Cheng Wen Wu; Chuang Cheng; Shao I. Chen; Chi Yi Hwang; Hsiao Ping Lin

doi:10.1109/MM.2002.1044301

A hierarchical test methodology for systems on chip

Jin Fu Li
, Hsin Jung Huang
, Jeng Bin Chen
, Chih Pin Su
, Cheng Wen Wu
, Chuang Cheng
, Shao I. Chen
, Chi Yi Hwang
, Hsiao Ping Lin

電機工程學系

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

原文	English
頁（從 - 到）	69-81
頁數	13
期刊	IEEE Micro
卷	22
發行號	5
DOIs	https://doi.org/10.1109/MM.2002.1044301
出版狀態	Published - 2002 9月 1

All Science Journal Classification (ASJC) codes

電腦繪圖與電腦輔助設計
硬體和架構
軟體

存取文件

10.1109/MM.2002.1044301

其它文件與鏈接

引用此

@article{7d9f59cce924431180e6040a573d125b,

title = "A hierarchical test methodology for systems on chip",

author = "Li, \{Jin Fu\} and Huang, \{Hsin Jung\} and Chen, \{Jeng Bin\} and Su, \{Chih Pin\} and Wu, \{Cheng Wen\} and Chuang Cheng and Chen, \{Shao I.\} and Hwang, \{Chi Yi\} and Lin, \{Hsiao Ping\}",

year = "2002",

month = sep,

day = "1",

doi = "10.1109/MM.2002.1044301",

language = "English",

volume = "22",

pages = "69--81",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "5",

}

TY - JOUR

T1 - A hierarchical test methodology for systems on chip

AU - Li, Jin Fu

AU - Huang, Hsin Jung

AU - Chen, Jeng Bin

AU - Su, Chih Pin

AU - Wu, Cheng Wen

AU - Cheng, Chuang

AU - Chen, Shao I.

AU - Hwang, Chi Yi

AU - Lin, Hsiao Ping

PY - 2002/9/1

Y1 - 2002/9/1

UR - https://www.scopus.com/pages/publications/0036760593

UR - https://www.scopus.com/pages/publications/0036760593#tab=citedBy

U2 - 10.1109/MM.2002.1044301

DO - 10.1109/MM.2002.1044301

M3 - Article

AN - SCOPUS:0036760593

SN - 0272-1732

VL - 22

SP - 69

EP - 81

JO - IEEE Micro

JF - IEEE Micro

IS - 5

ER -