TY - GEN
T1 - A High Performance Accelerating CNN Inference on FPGA with Arrhythmia Classification
AU - Ku, Ming Yueh
AU - Zhong, Tai Siang
AU - Hsieh, Yi Ting
AU - Lee, Shuenn Yuh
AU - Chen, Ju Yi
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - A high-performance artificial intelligence accelerator (AIA) for arrhythmia classification on electrocardiography (ECG) is presented in this paper, which proposes an efficient one-dimensional convolutional neural network (1DCNN) with novel multiplicative behavioral and data reuse. The convolutional layer uses weight stationary (WS) to achieve low memory access on tensor-tensor multiplication (TTM) operations and the fully connected layer uses input stationary (IS) to achieve low memory access on inner product matrix-vector multiplication (IPMVM). The lab database and MIT-BIH arrhythmia database are selected to verify the proposed algorithm. The accuracy of software simulation classification on two databases is 97.3% and 98.3%, respectively. Combined with the hardware implementation of quantization and pruned with the architecture of parallel shift processing element array arrangement (PSPEAA) proposed in this work, the accuracies are 96.6% and 96.5%, respectively. The hardware is implemented on Xilinx PYNQ-Z2, and it takes only 0.233 ms operated at 10 MHz and consumes 0.131 W to classify arrhythmia. Finally, according to the proposed technology, the time of memory access is optimized by 29 times and latency is optimized by 22.5 times compared to using a single multiply-accumulate (MAC). Therefore, the proposed architecture can achieve real-time low-power consumption and high-accuracy arrhythmia classification.
AB - A high-performance artificial intelligence accelerator (AIA) for arrhythmia classification on electrocardiography (ECG) is presented in this paper, which proposes an efficient one-dimensional convolutional neural network (1DCNN) with novel multiplicative behavioral and data reuse. The convolutional layer uses weight stationary (WS) to achieve low memory access on tensor-tensor multiplication (TTM) operations and the fully connected layer uses input stationary (IS) to achieve low memory access on inner product matrix-vector multiplication (IPMVM). The lab database and MIT-BIH arrhythmia database are selected to verify the proposed algorithm. The accuracy of software simulation classification on two databases is 97.3% and 98.3%, respectively. Combined with the hardware implementation of quantization and pruned with the architecture of parallel shift processing element array arrangement (PSPEAA) proposed in this work, the accuracies are 96.6% and 96.5%, respectively. The hardware is implemented on Xilinx PYNQ-Z2, and it takes only 0.233 ms operated at 10 MHz and consumes 0.131 W to classify arrhythmia. Finally, according to the proposed technology, the time of memory access is optimized by 29 times and latency is optimized by 22.5 times compared to using a single multiply-accumulate (MAC). Therefore, the proposed architecture can achieve real-time low-power consumption and high-accuracy arrhythmia classification.
UR - http://www.scopus.com/inward/record.url?scp=85166376537&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85166376537&partnerID=8YFLogxK
U2 - 10.1109/AICAS57966.2023.10168615
DO - 10.1109/AICAS57966.2023.10168615
M3 - Conference contribution
AN - SCOPUS:85166376537
T3 - AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding
BT - AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2023
Y2 - 11 June 2023 through 13 June 2023
ER -