A high-performance SoC debug platform

Kuo Kai Liu, Wen Hsuan Hsu, Kuen Jong Lee

研究成果: Article同行評審

摘要

The vast increasing complexity of SoC design makes chip verification and debugging an extremely difficult task. In this paper we present a highly efficient run-stop-resume based SoC Debug Platform to deal with this problem. This platform allows one to observe any signals in the Intellectual Properties (IPs) of a SoC system during the normal system by implanting three powerful debug-trigger mechanisms into the SoC, namely cycle-based, event-based, and hardware-software cross-trigger-based mechanisms. With this platform, both hardware and software designers can work together on a common debugging environment from the very beginning so as to greatly increase debugging efficiency. Furthermore, we have also developed a design automation program called DASDEP (Design Automation System for SoC DEbug Platfrom) that can help users add design-for-debug circuitry into the SoC design and setup the required debug environment. DASDEP also provides a user-friendly interface for the whole debug process. This program together with the three debug mechanisms allows the SoC verification and debugging to be accomplished much more easily and efficiently than the conventional debug methods.

原文English
頁(從 - 到)202-208
頁數7
期刊Smart Science
3
發行號4
DOIs
出版狀態Published - 2015 一月 1

All Science Journal Classification (ASJC) codes

  • 化學(雜項)
  • 建模與模擬
  • 能源(雜項)
  • 工程 (全部)
  • 流體流動和轉移過程
  • 電腦網路與通信
  • 計算數學

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