The vast increasing complexity of SoC design makes chip verification and debugging an extremely difficult task. In this paper we present a highly efficient run-stop-resume based SoC Debug Platform to deal with this problem. This platform allows one to observe any signals in the Intellectual Properties (IPs) of a SoC system during the normal system by implanting three powerful debug-trigger mechanisms into the SoC, namely cycle-based, event-based, and hardware-software cross-trigger-based mechanisms. With this platform, both hardware and software designers can work together on a common debugging environment from the very beginning so as to greatly increase debugging efficiency. Furthermore, we have also developed a design automation program called DASDEP (Design Automation System for SoC DEbug Platfrom) that can help users add design-for-debug circuitry into the SoC design and setup the required debug environment. DASDEP also provides a user-friendly interface for the whole debug process. This program together with the three debug mechanisms allows the SoC verification and debugging to be accomplished much more easily and efficiently than the conventional debug methods.
All Science Journal Classification (ASJC) codes
- 工程 (全部)