A high-performance unified-field reconfigurable cryptographic processor

Jun Hong Chen, Ming-Der Shieh, Wen Ching Lin

研究成果: Article

25 引文 (Scopus)

摘要

With rapid increases in communication and network applications, cryptography has become a crucial issue to ensure the security of transmitted data. In this paper, we propose a microcode-based architecture with a novel reconfigurable datapath which can perform either prime field GF(p) operations or binary extension field GF(2 m ) operations for arbitrary prime numbers, irreducible polynomials, and precision. Using these field arithmetic units, users are capable of programming cryptographic algorithms in microcode sequences for full compliance with a majority of public-key cryptographic algorithms such as RivestShamirAdleman (RSA) and elliptic curve cryptosystems. An algorithmic optimization or refinement can thus be made at a higher level based on the reconfigurable datapath. Experimental results show that the developed processor has full cryptography algorithm flexibility, high hardware utilization, and high performance.

原文English
文章編號5325648
頁(從 - 到)1145-1158
頁數14
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
18
發行號8
DOIs
出版狀態Published - 2010 八月 1

指紋

Cryptography
Firmware
Security of data
Computer programming
Computer hardware
Polynomials
Communication
Compliance

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

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A high-performance unified-field reconfigurable cryptographic processor. / Chen, Jun Hong; Shieh, Ming-Der; Lin, Wen Ching.

於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷 18, 編號 8, 5325648, 01.08.2010, p. 1145-1158.

研究成果: Article

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