A high-speed and memory efficient pipeline architecture for packet classification

Yeim-Kuan Chang, Yi Shang Lin, Cheng Chien Su

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

Multi-field Packet classification is the main function in high-performance routers. The current router design goal of achieving a throughput higher than 40 Gbps and supporting large rule sets simultaneously is difficult to be fulfilled by software approaches. In this paper, a set pruning trie based pipelined architecture called Set Pruning Multi-Bit Trie (SPMT) is proposed for multi-field packet classification. However, the problem of rule duplications in SPMT that may cause a memory blowup must be solved in order to implement SPMT with large rule sets in FPGA devices consisting of limited on-chip memory. We will propose two rule grouping schemes to reduce rule duplications in SPMT. The first scheme called Partition by Wildcards (PW) divides the rules into subgroups based on the positions of their wildcard fields. The second scheme called Partition by Length (PL) rules partitions the rules into subgroups according to their prefix lengths. Based on our performance experiments on Xilinx Virtex-5 FPGA device, the proposed pipeline architecture can achieve a throughput of over 100 Gbps with dual port memory. Also, the rule sets of up to 10k rules can be fit into the on-chip memory of Xilinx Virtex-5 FPGA device.

原文English
主出版物標題Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010
頁面215-218
頁數4
DOIs
出版狀態Published - 2010 七月 9
事件18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010 - Charlotte, NC, United States
持續時間: 2010 五月 22010 五月 4

出版系列

名字Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

Other

Other18th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010
國家United States
城市Charlotte, NC
期間10-05-0210-05-04

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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