A high speed BIST architecture for DDR-SDRAM testing

In this paper, we propose a high speed Built-In Self-Test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A novel scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired march algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18um technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design.