摘要
In this paper, we propose a high speed Built-In Self-Test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A novel scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired march algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18um technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design.
| 原文 | English |
|---|---|
| 主出版物標題 | Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 |
| 頁面 | 52-57 |
| 頁數 | 6 |
| DOIs | |
| 出版狀態 | Published - 2005 十二月 9 |
| 事件 | Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan 持續時間: 2005 八月 3 → 2005 八月 5 |
出版系列
| 名字 | Records of the IEEE International Workshop on Memory Technology, Design and Testing |
|---|---|
| ISSN（列印） | 1087-4852 |
Other
| Other | Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 |
|---|---|
| 國家 | Taiwan |
| 城市 | Taipei |
| 期間 | 05-08-03 → 05-08-05 |
指紋
All Science Journal Classification (ASJC) codes
- Media Technology
引用此文
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A high speed BIST architecture for DDR-SDRAM testing. / Shen, Sheng-Chih; Hsu, Hung Ming; Chang, Yi Wei; Lee, Kuen-Jong.
Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. 2005. p. 52-57 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).研究成果: Conference contribution
TY - GEN
T1 - A high speed BIST architecture for DDR-SDRAM testing
AU - Shen, Sheng-Chih
AU - Hsu, Hung Ming
AU - Chang, Yi Wei
AU - Lee, Kuen-Jong
PY - 2005/12/9
Y1 - 2005/12/9
N2 - In this paper, we propose a high speed Built-In Self-Test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A novel scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired march algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18um technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design.
AB - In this paper, we propose a high speed Built-In Self-Test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A novel scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired march algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18um technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design.
UR - http://www.scopus.com/inward/record.url?scp=28344439193&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=28344439193&partnerID=8YFLogxK
U2 - 10.1109/MTDT.2005.9
DO - 10.1109/MTDT.2005.9
M3 - Conference contribution
AN - SCOPUS:28344439193
SN - 0769523137
T3 - Records of the IEEE International Workshop on Memory Technology, Design and Testing
SP - 52
EP - 57
BT - Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
ER -