A high speed BIST architecture for DDR-SDRAM testing

Sheng-Chih Shen, Hung Ming Hsu, Yi Wei Chang, Kuen-Jong Lee

研究成果: Conference contribution

8 引文 (Scopus)

摘要

In this paper, we propose a high speed Built-In Self-Test (BIST) design which can support the at-speed testing for DDR or DDR2 SDRAM. We use the pipeline strategy together with several special design techniques to achieve the high speed requirement. A novel scheme is developed which can efficiently solve the problem of different execution cycles of DDR or DDR2 SDRAM's commands and can generate a compact test sequence for the desired march algorithm(s). Our BIST can support single or multiple March algorithms. With the single algorithm design extremely high speed around 833 MHz is achieved using the TSMC 0.18um technology. For the multiple-algorithms design, our design can still satisfy the speed requirement of DDR2 memory even with the 3 most complex March algorithms. Our experiment also shows that if only DDR memory testing is required, then more than 30 March algorithms can be integrated into our BIST design.

原文English
主出版物標題Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
頁面52-57
頁數6
DOIs
出版狀態Published - 2005 十二月 9
事件Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan
持續時間: 2005 八月 32005 八月 5

出版系列

名字Records of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN(列印)1087-4852

Other

OtherProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
國家Taiwan
城市Taipei
期間05-08-0305-08-05

指紋

Built-in self test
Testing
Data storage equipment
Pipelines
Experiments

All Science Journal Classification (ASJC) codes

  • Media Technology

引用此文

Shen, S-C., Hsu, H. M., Chang, Y. W., & Lee, K-J. (2005). A high speed BIST architecture for DDR-SDRAM testing. 於 Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 (頁 52-57). (Records of the IEEE International Workshop on Memory Technology, Design and Testing). https://doi.org/10.1109/MTDT.2005.9
Shen, Sheng-Chih ; Hsu, Hung Ming ; Chang, Yi Wei ; Lee, Kuen-Jong. / A high speed BIST architecture for DDR-SDRAM testing. Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. 2005. 頁 52-57 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).
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Shen, S-C, Hsu, HM, Chang, YW & Lee, K-J 2005, A high speed BIST architecture for DDR-SDRAM testing. 於 Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. Records of the IEEE International Workshop on Memory Technology, Design and Testing, 頁 52-57, Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005, Taipei, Taiwan, 05-08-03. https://doi.org/10.1109/MTDT.2005.9

A high speed BIST architecture for DDR-SDRAM testing. / Shen, Sheng-Chih; Hsu, Hung Ming; Chang, Yi Wei; Lee, Kuen-Jong.

Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. 2005. p. 52-57 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

研究成果: Conference contribution

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Shen S-C, Hsu HM, Chang YW, Lee K-J. A high speed BIST architecture for DDR-SDRAM testing. 於 Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. 2005. p. 52-57. (Records of the IEEE International Workshop on Memory Technology, Design and Testing). https://doi.org/10.1109/MTDT.2005.9