TY - GEN
T1 - A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique
AU - Lin, Jin Fu
AU - Chang, Soon Jyh
PY - 2006
Y1 - 2006
N2 - In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.
AB - In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the highlinearity requirement of the op-amp, a new type of SHA circuit is presented.
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M3 - Conference contribution
AN - SCOPUS:34547324226
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 5367
EP - 5370
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -