A high-speed rail-to-rail output buffer with push-pull dual-path and dynamic-bias for LCD driver ICs

Chien Hung Tsai, Jia Hui Wang

研究成果: Article同行評審

摘要

The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push-pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 9 48 μm2.

原文English
頁(從 - 到)303-310
頁數8
期刊Analog Integrated Circuits and Signal Processing
70
發行號3
DOIs
出版狀態Published - 2012 三月

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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