The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push-pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 9 48 μm2.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films