A high-throughput low-cost AES cipher chip

Tsung Fu Lin, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

34 引文 斯高帕斯(Scopus)

摘要

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

原文English
主出版物標題2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面85-88
頁數4
ISBN(電子)0780373634, 9780780373631
DOIs
出版狀態Published - 2002 一月 1
事件3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
持續時間: 2002 八月 62002 八月 8

出版系列

名字2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
國家Taiwan
城市Taipei
期間02-08-0602-08-08

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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