A hybrid self-testing methodology of processor cores

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new SBST methodology that uses information abstracted from the processor instruction set architecture (ISA), pipeline architecture model, RTL descriptions, and gate-level net-list for test program development of different types of the processor circuitry. This paper demonstrates the feasibility of the proposed methodology by the achieved fault coverage on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.

原文English
主出版物標題2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
頁面3378-3381
頁數4
DOIs
出版狀態Published - 2008 九月 19
事件2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
持續時間: 2008 五月 182008 五月 21

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
國家United States
城市Seattle, WA
期間08-05-1808-05-21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • 引用此

    Lu, T. H., Chen, C-H., & Lee, K-J. (2008). A hybrid self-testing methodology of processor cores. 於 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (頁 3378-3381). [4542183] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4542183