A low-cost and scalable test architecture for multi-core chips

Chun Chuan Chi, Cheng Wen Wu, Jin Fu Li

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.

原文English
主出版物標題2010 15th IEEE European Test Symposium, ETS'10
頁面30-35
頁數6
DOIs
出版狀態Published - 2010 十一月 3
事件2010 15th IEEE European Test Symposium, ETS'10 - Prague, Czech Republic
持續時間: 2010 五月 242010 五月 28

出版系列

名字2010 15th IEEE European Test Symposium, ETS'10

Conference

Conference2010 15th IEEE European Test Symposium, ETS'10
國家Czech Republic
城市Prague
期間10-05-2410-05-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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