A low-cost bit-error-rate BIST circuit for high-speed ADCs based on gray coding

Ya Ting Shyu, Ying Zu Lin, Rong Sing Chu, Guan Ying Huang, Soon Jyh Chang

研究成果: Article同行評審

摘要

Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented method takes the advantages of Gray coding and only needs simple logic circuits for BER evaluation. The prototype of the BIST circuit is fabricated along with a 5-bit high-speed flash ADC in a 90-nm CMOS process. The active area is only 90 μm × 70 μm and the average power consumption is around 0.3mW at 700MS/s. The measurement of the BIST circuit shows consistent results with the measurement by external data acquisition equipment.

原文English
頁(從 - 到)2415-2423
頁數9
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
發行號12
DOIs
出版狀態Published - 2012 十二月

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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