A low-cost output response analyzer circuit for ADC BIST

Hsin Wen Ting, I. Jen Chao, Yu Chang Lien, Soon Jyh Chang, Bin Da Liu

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a low-cost ADC output response analyzer (ORA) circuit for built-in self-test (BIST) application is proposed. The sine-wave histogram testing method and the basic COordinate Rotation Digital Computer (CORDIC) technique are used to design the proposed ADC ORA circuit. The ADC's static and dynamic parameters can both be obtained using the proposed circuit. The basic CORDIC based ADC ORA circuit is designed and synthesized in a 0.18-uμm technology to analyze the outputs an 8-bit ADC to verify the designs. It shows a lower area overhead compared with the Fast Fourier transform (FFT) based realization.

原文English
主出版物標題2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
DOIs
出版狀態Published - 2009 九月 17
事件2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 - Chengdu, China
持續時間: 2009 四月 282009 四月 29

出版系列

名字2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Other

Other2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
國家China
城市Chengdu
期間09-04-2809-04-29

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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