A low-cost output response analyzer circuit for ADC BIST

Hsin Wen Ting; I. Jen Chao; Yu Chang Lien; Soon Jyh Chang; Bin Da Liu

doi:10.1109/CAS-ICTD.2009.4960751

A low-cost output response analyzer circuit for ADC BIST

Hsin Wen Ting
, I. Jen Chao
, Yu Chang Lien
, Soon Jyh Chang
, Bin Da Liu

電機工程學系

研究成果: Conference contribution

1 引文斯高帕斯（Scopus）

摘要

In this paper, a low-cost ADC output response analyzer (ORA) circuit for built-in self-test (BIST) application is proposed. The sine-wave histogram testing method and the basic COordinate Rotation Digital Computer (CORDIC) technique are used to design the proposed ADC ORA circuit. The ADC's static and dynamic parameters can both be obtained using the proposed circuit. The basic CORDIC based ADC ORA circuit is designed and synthesized in a 0.18-uμm technology to analyze the outputs an 8-bit ADC to verify the designs. It shows a lower area overhead compared with the Fast Fourier transform (FFT) based realization.

原文	English
主出版物標題	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
DOIs	https://doi.org/10.1109/CAS-ICTD.2009.4960751
出版狀態	Published - 2009 9月 17
事件	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 - Chengdu, China 持續時間: 2009 4月 28 → 2009 4月 29

出版系列

名字	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Other

Other	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
國家/地區	China
城市	Chengdu
期間	09-04-28 → 09-04-29

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程
建模與模擬

存取文件

10.1109/CAS-ICTD.2009.4960751

其它文件與鏈接

引用此

Ting, H. W., Chao, I. J., Lien, Y. C., Chang, S. J., & Liu, B. D. (2009). A low-cost output response analyzer circuit for ADC BIST. 於 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 文章 4960751 (2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09). https://doi.org/10.1109/CAS-ICTD.2009.4960751

@inproceedings{e5f05d226c324d7cb9b3aea6ae8c0ea3,

title = "A low-cost output response analyzer circuit for ADC BIST",

abstract = "In this paper, a low-cost ADC output response analyzer (ORA) circuit for built-in self-test (BIST) application is proposed. The sine-wave histogram testing method and the basic COordinate Rotation Digital Computer (CORDIC) technique are used to design the proposed ADC ORA circuit. The ADC's static and dynamic parameters can both be obtained using the proposed circuit. The basic CORDIC based ADC ORA circuit is designed and synthesized in a 0.18-uμm technology to analyze the outputs an 8-bit ADC to verify the designs. It shows a lower area overhead compared with the Fast Fourier transform (FFT) based realization.",

author = "Ting, \{Hsin Wen\} and Chao, \{I. Jen\} and Lien, \{Yu Chang\} and Chang, \{Soon Jyh\} and Liu, \{Bin Da\}",

year = "2009",

month = sep,

day = "17",

doi = "10.1109/CAS-ICTD.2009.4960751",

language = "English",

isbn = "9781424425877",

series = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",

booktitle = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",

note = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 ; Conference date: 28-04-2009 Through 29-04-2009",

}

Ting, HW, Chao, IJ, Lien, YC, Chang, SJ & Liu, BD 2009, A low-cost output response analyzer circuit for ADC BIST. 於 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09., 4960751, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, Chengdu, China, 09-04-28. https://doi.org/10.1109/CAS-ICTD.2009.4960751

TY - GEN

T1 - A low-cost output response analyzer circuit for ADC BIST

AU - Ting, Hsin Wen

AU - Chao, I. Jen

AU - Lien, Yu Chang

AU - Chang, Soon Jyh

AU - Liu, Bin Da

PY - 2009/9/17

Y1 - 2009/9/17

N2 - In this paper, a low-cost ADC output response analyzer (ORA) circuit for built-in self-test (BIST) application is proposed. The sine-wave histogram testing method and the basic COordinate Rotation Digital Computer (CORDIC) technique are used to design the proposed ADC ORA circuit. The ADC's static and dynamic parameters can both be obtained using the proposed circuit. The basic CORDIC based ADC ORA circuit is designed and synthesized in a 0.18-uμm technology to analyze the outputs an 8-bit ADC to verify the designs. It shows a lower area overhead compared with the Fast Fourier transform (FFT) based realization.

AB - In this paper, a low-cost ADC output response analyzer (ORA) circuit for built-in self-test (BIST) application is proposed. The sine-wave histogram testing method and the basic COordinate Rotation Digital Computer (CORDIC) technique are used to design the proposed ADC ORA circuit. The ADC's static and dynamic parameters can both be obtained using the proposed circuit. The basic CORDIC based ADC ORA circuit is designed and synthesized in a 0.18-uμm technology to analyze the outputs an 8-bit ADC to verify the designs. It shows a lower area overhead compared with the Fast Fourier transform (FFT) based realization.

UR - https://www.scopus.com/pages/publications/70149098935

UR - https://www.scopus.com/pages/publications/70149098935#tab=citedBy

U2 - 10.1109/CAS-ICTD.2009.4960751

DO - 10.1109/CAS-ICTD.2009.4960751

M3 - Conference contribution

AN - SCOPUS:70149098935

SN - 9781424425877

T3 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

BT - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

T2 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Y2 - 28 April 2009 through 29 April 2009

ER -

A low-cost output response analyzer circuit for ADC BIST

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All Science Journal Classification (ASJC) codes

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