A low dropout linear regulator with high power supply rejection

Huei Sheng Jhuang, Jia Hui Wang, Zi Yu Zeng, Chien-Hung Tsai

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

Combining the supply ripple subtraction and high-pass filtering can improve the power supply rejection (PSR) over wideband frequency of low dropout regulator (LDO). The proposed LDO is fabricated by TSMC 0.35μm 2-poly 4-metal CMOS process. The simulation results at maximum load current of 100mA, show that PSR at 10k, 100k and 1M are -72dB, -75dB and -46dB,respectively. Therefore, it's well suited for switching pre-regulator and SoC applications. The active area of this LDO is 300x360μm2.

原文English
主出版物標題ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
頁面41-44
頁數4
出版狀態Published - 2009
事件12th International Symposium on Integrated Circuits, ISIC-2009 - Singapore, Singapore
持續時間: 2009 12月 142009 12月 16

Other

Other12th International Symposium on Integrated Circuits, ISIC-2009
國家/地區Singapore
城市Singapore
期間09-12-1409-12-16

All Science Journal Classification (ASJC) codes

  • 計算機理論與數學
  • 電腦繪圖與電腦輔助設計
  • 硬體和架構
  • 電氣與電子工程

指紋

深入研究「A low dropout linear regulator with high power supply rejection」主題。共同形成了獨特的指紋。

引用此