A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window

Chih Yuan Kung, Chun Po Huang, Chia Chuan Li, Soon Jyh Chang

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique also uses the transient information to produce AW for each bit which can significantly reduce the power consumption of the comparator, the DAC settling time and also digital control logic. Last but not least, the timing control window can also avoid ADC from encountering meta-stability. The measurement result achieves an SNDR of 57.18 dB, an ENOB of 9.2 bits, a power consumption of 74 nW, and a resulting FoM of 1.25 fJ/conv.-step.

原文English
主出版物標題2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538648810
DOIs
出版狀態Published - 2018 四月 26
事件2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
持續時間: 2018 五月 272018 五月 30

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(列印)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
國家Italy
城市Florence
期間18-05-2718-05-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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