A low-latency compression architecture for memory i/o link on GPGPU

Meng Yang Lu, Yu An Lai, Chih Hung Kuo

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

With the advance of contemporary computer architectures, there is a continuously growing performance gap between processors and memories. Data compression is a promising approach to resolve this issue by reducing the data size. On general-purpose graphics processing unit (GPGPU), many parallel computing applications have large amounts of floating-point data. In this paper, we propose an innovative compression algorithm with low latency by exploiting regular data patterns. By integrating the proposed architecture with the memory controller, the GPU can averagely reduce 44.46% of the memory bandwidth usage, and reduce 44.34% of the energy consumption.

原文English
頁(從 - 到)203-210
頁數8
期刊International Journal of Electrical Engineering
26
發行號5
DOIs
出版狀態Published - 2019 十月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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