A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation

Fang Yi Gu, Ing Chao Lin, Jia Wei Lin

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)


Multipliers are among the most critical arithmetic functional units in many applications, and those applications commonly require many multiplications which result in significant power consumption. For applications that have error tolerance, employing an approximate multiplier is an emerging method to reduce critical path delay and power consumption. An approximate multiplier can trade off accuracy for lower energy and higher performance. In this paper, we not only propose an approximate 4-2 compressor with high accuracy, but also an adjustable approximate multiplier that can dynamically truncate partial products to achieve variable accuracy requirements. In addition, we also propose a simple error compensation circuit to reduce error distance. The proposed approximate multiplier can adjust the accuracy and power required for multiplications at run-time based on the users' requirement. Experimental results show that the delay and the average power consumption of the proposed adjustable approximate multiplier can be reduced by 27% and 40.33% (up to 72%) when compared to the Wallace tree multiplier. Moreover, we demonstrate the suitability and reconfigurability of our proposed multiplier in convolutional neural networks (CNNs) to meet different requirements at each layer.

頁(從 - 到)60447-60458
期刊IEEE Access
出版狀態Published - 2022

All Science Journal Classification (ASJC) codes

  • 電腦科學(全部)
  • 材料科學(全部)
  • 工程 (全部)


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